Contact one of the authors (ranga.vemuriffluc.edu or nandfflthor.ece.uc.edu) if you are interested in obtaining these examples. ...  R. Ernst and J. Bhasker, aquot; Simulation-based verification for high-level synthesisaquot; , IEEE Design aamp; Test of Computers, Vol. ... 171 R. Jain and B. Richards, LagerlV users manual, University of California at Berkeley. ... 26] J. Roy and R. Vemuri aquot;The VSS Intermediate Format (VIF)aquot;, Design Memo, Lab. for Digital Design Environments, University of Cincinnati, anbsp;...
|Title||:||30th Design Automation Conference|