A 90nm 64Kb SRAM module is designed and used as an example to demonstrate the prediction methodology. With the given application profile, simulation results showed that TDDB is the most serious reliability concern for the SRAM bit cell, NBTI is in the second place, and HCD has a negligible degradation effect. The memory core's reliability prediction shows the core has a low constant failure rate (2.90E-4 FIT) before 5.8E+4 hours, and an increasing failure rate after that because NBTI wearout starts to kick in.Script ocnWaveformTool( a#39;wavescan ) simulator( a#39;spectre ) design (aquot; /homes /qjin/ cadence / simulation / SRAM ... /homes /qjin/ cadence / simulation / SRAM / spectre /schematicaquot; ) modelFile( a#39; (aquot; /users/qjin /home/cadence/SRAM /ibmO 13um.txtaquot;anbsp;...
|Title||:||A New Physics-of-failure Based VLSI Circuits Reliability Simulation and Prediction Methodology|
|Publisher||:||ProQuest - 2007|