Integrating formal property verification (FPV) into an existing design process raises several interesting questions. This book develops the answers to these questions and fits them into a roadmap for formal property verification a a roadmap that shows how to glue FPV technology into the traditional validation flow. The book explores the key issues in this powerful technology through simple examples that mostly require no background on formal methods.For example, there are several choice points for the test environment of a AMBA AHB slave interface. ... Recent test bench languages such as the test bench language of SystemVerilog enables a validation engineer to specify the coverage anbsp;...
|Title||:||A Roadmap for Formal Property Verification|
|Publisher||:||Springer Science & Business Media - 2007-01-19|