Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todayas digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model qoff-the-shelfq or qIPq digital components for use in FPGA and board-level design verification.Many netlisters will find an attribute attached to some special object in the schematic, such as the schematic border, and ... The payoff for writing component simulation models comes when they are integrated into a schematic capture system and used for board-level verification. ... In the example it is assumed that Cadencea#39;s Allegro is used for PCB layout and Mentora#39;s ModelSim is used for simulation.
|Title||:||ASIC and FPGA Verification|
|Publisher||:||Academic Press - 2004-10-23|