Co-verification of Hardware and Software for ARM SoC Design

Co-verification of Hardware and Software for ARM SoC Design

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Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core - a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools. * The only book on verification for systems-on-a-chip (SoC) on the market * Will save engineers and their companies time and money by showing them how to speed up the testing process, while still avoiding costly mistakes * Design examples use the ARM core, the dominant technology in SoC, and all the source code is included on the accompanying CD-Rom, so engineers can easily use it in their own designs... 172, 174, 175, 177, 232, 235, 249, 250, 251 optimized memory, 171, 174 organizational structure, 18 OVI (Open Verilog International), 27 ... 7 registers, 63 regular expression, 209 reliability, 8 remote debugging, 43 remote protocol interface, 145 reset, 80, 81, 98 reset vector, ... 214 Simulation Technologies, xv, 123 simulation timestamp, 55, 66, 189, 190, 191, 192 single-layer AHB, 107, 108, 158 slave, anbsp;...

Title:Co-verification of Hardware and Software for ARM SoC Design
Author:Jason Andrews
Publisher:Elsevier - 2004-09-04


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