Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

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The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.Obvious improvements would include taking a considerably larger set of data and taking contacts into account. Furthermore, the ... Despite all these shortcomings, it is clear that the prediction is in the correct order, and a trend can be observed: more weak opens result in more delay faults. ... Benevolent defects are the ones that change the shape of the silicon layer structure yet they do not cause a fault.

Title:Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Author:Manoj Sachdev, Jose Pineda de Gyvez
Publisher:Springer Science & Business Media - 2007-06-04


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