ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As the problems associated with ESD failures and yield losses become significant in the modern semiconductor industry, the demand for graduates with a basic knowledge of ESD is also increasing. Today, there is a significant demand to educate the circuits design and reliability teams on ESD issues. This book makes an attempt to address the ESD design and implementation in a systematic manner. A design procedure involving device simulators as well as circuit simulator is employed to optimize device and circuit parameters for optimal ESD as well as circuit performance. This methodology, described in ESD Protection Device and Circuit Design for Advanced CMOS Technologies has resulted in several successful ESD circuit design with excellent silicon results and demonstrates its strengths.Typically, the gain of the npn transistor is an order of magnitude higher than that of the pnp transistor. Therefore, the npn transistor turns on easily compared to the pnp transistor. When the npn transistor turns on, its current generates a voltageanbsp;...
|Title||:||ESD Protection Device and Circuit Design for Advanced CMOS Technologies|
|Author||:||Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev|
|Publisher||:||Springer Science & Business Media - 2008-04-26|