For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore's law into remarkable increases in performance. Recently, however, the bounty provided by Moore's law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults. In this book, we focus on the dependability challenge and the fault tolerance solutions that architects are developing to overcome it. The two main purposes of this book are to explore the key ideas in fault-tolerant computer architecture and to present the current state-of-the-art - over approximately the past 10 years - in academia and industry. Table of Contents: Introduction / Error Detection / Error Recovery / Diagnosis / Self-Repair / The FutureBecause of the array-like layout of storage structures, performing self- repair at the row and column granularity is far easier than repairing arbitrary groups of bits. ...  developed two schemes for tolerating large numbers of faulty cache cells and thus enabling voltage reductions. ... Sonya#39;s PlayStation 3 explicitly uses only seven of the eight synergistic processing element (SPE) cores in the Cellanbsp;...
|Title||:||Fault Tolerant Computer Architecture|
|Publisher||:||Morgan & Claypool Publishers - 2009-07-08|