Design Summery V. CONCLUSION AND FUTURE SCOPE A DHT transform of 8 bit input is being implemented with radix 4 implementation. ... FFT has consumed 8 adders 4 multipliers where as the proposed scheme has only 4 adders and 2 sharing multipliers as one of the twiddle factor is one. Implementation is done in verilog language using Xilinx tool. ... Member, IEEE, aA Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecturea, IEEE Transactions on Circuits andanbsp;...
|Title||:||International Conference on Advances in Engineering and Technology ,hyderabad|
|Publisher||:||INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY FOR SKILL DEVELOPMENT -|