Proceedings IEEE computer society. 4.1. Configuration of ... them as a synchronous reset by eliminating the signal from a sensitivity list of an always statement of Verilog-HDL since they are controlled from primary inputs directly. ac The interfaceanbsp;...
|Title||:||International Conference on Computer Design|
|Author||:||IEEE computer society|
|Publisher||:||Institute of Electrical & Electronics Engineers(IEEE) - 1998|