For main stream acceptance of asynchronous circuits, a mature EDA tool flow is necessary that leverages off commercially available libraries and tools for synchronous circuits. Many asynchronous templates however rely on specialized and complex circuits that are not present in commercial libraries. For such templates, designers either technology map these cells to existing libraries at the cost of area and performance or rely on full-custom design and extensive SPICE simulation to verity timing correctness and performance. This thesis addresses both of these issues by developing both library characterization and static timing analysis flows for non-standard asynchronous circuit templates that together support back-annotated power and timing simulations as well as static timing and performance verification. We first create a fully-automated characterization flow for the static single-track full-buffers template. We then develop a fully-automated static-timing flow for timing and performance verification using the gold-standard commercial tool, Synopsys PrimeTime. The proposed flow is successfully demonstrated on three different asynchronous design styles.It then describes a novel methodology and tool kit to automatically characterize the library and represent the ... verify all relative timing assumptions (e.g., isochronic forks) as well as the gate-level performance of any circuit designed with theseanbsp;...
|Title||:||Library Characterization and Static Timing Analysis of Asynchronous Circuits|
|Publisher||:||ProQuest - 2007|