At the hardware level, this thesis presents a technique for detecting faults in the processor control logic, for which techniques proposed previously incur very high overheads. Rather than detect all modeled faults, the technique protects against a subset of faults such that the best possible overall protection is achieved while incurring only permissible overheads. This subset of faults is selected depending on the probability of each individual fault causing damage to the architectural state of the processor and the overhead incurred in protecting against the fault. The technique is validated on control logic modules of an industrial processor.For each error that needs to be injected, the UML virtual machine was run once. Each run of ... 54.7% of the errors resulted in the operating system crashing due to segmentation faults, illegal instruction faults, and arithmetic exceptions. 9.3% ofanbsp;...
|Title||:||Low-cost Assertion-based Fault Tolerance in Hardware and Software|
|Publisher||:||ProQuest - 2008|