Processor Architecture

Processor Architecture

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Today's microprocessors are the powerful descendants of the von Neumann 1 computer dating back to a memo of Burks, Goldstine, and von Neumann of 1946. The so-called von Neumann architecture is characterized by a se quential control flow resulting in a sequential instruction stream. A program counter addresses the next instruction if the preceding instruction is not a control instruction such as, e. g. , jump, branch, subprogram call or return. An instruction is coded in an instruction format of fixed or variable length, where the opcode is followed by one or more operands that can be data, addresses of data, or the address of an instruction in the case of a control instruction. The opcode defines the types of operands. Code and data are stored in a common storage that is linear, addressed in units of memory words (bytes, words, etc. ). The overwhelming design criterion of the von Neumann computer was the minimization of hardware and especially of storage. The most simple implementation of a von Neumann computer is characterized by a microar chitecture that defines a closely coupled control and arithmetic logic unit (ALU), a storage unit, and an I/O unit, all connected by a single connection unit. The instruction fetch by the control unit alternates with operand fetches and result stores for the AL U.This solution, however, implies that instructions may not complete in the original program order (see Fig. 1.13). ... 1.13: q The mul instruction delays its write-back until the div instruction has written its result to the register which is ... Next we itemize several other pipelined RISC processors, including the Fairchild/ Intergraph Clipper, ARM, Hewlett-Packard PA- RISC, AMD 29000, and Motorola MC68000.

Title:Processor Architecture
Author:Jurij Silc, Borut Robic, Theo Ungerer
Publisher:Springer Science & Business Media - 1999-06-08


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