The utilization of single-port memory reduces the design complexities and area. Furthermore, memory arrays significantly reduce power compared with the delay elements used in some FFT processors. The switch-based architecture facilitates deactivating processing elements for power scalability. It also facilitates implementing different FFT sizes. The VLSI implementation of a non-pipeline switch-based processor is presented. Matlab simulations are conducted to analyze the performance. The timing, power and area results from RTL, synthesis and layout simulations are discussed and compared with other processors.16-point radix-2 DIF FFT 7 Figure 4 Dataflow for a Single Memory 64-point DIT FFT  9 Figure 5. Dataflow for a Cached FFT ... 16-Point FFT Butterfly Diagram with Intermediate Values 17 Figure 9. 16-Point FFT Butterfly ... Design Overview 68 Figure 31. ... Routing address and data in the design 74 Figure 34. The Three anbsp;...
|Title||:||Switch-based Fast Fourier Transform Processor|
|Publisher||:||ProQuest - 2008|