This thesis describes the implantation of a systematic quasi-cyclic block code that detects and corrects two bit errors in digital data in a programmable logic controller. The implementation uses parity bits derived from a generator matrix to develop encoding and decoding schemes in ladder logic to test and correct any random single or double bit error. Implemented ladder logic and syndrome patterns are presented for demonstration and evaluation purposes.... Automationa#39;s RSLogix 500 programming and display software with RSLinx as the communications package for the necessary communications drivers running on a Dell Latitude laptop computer. THE NEED FOR ERROR DETECTION In aanbsp;...
|Title||:||Using a Programmable Logic Controller to Implement a (16,8) 2-bit Error Detection and Correction Code|
|Publisher||:||ProQuest - 2007|