This dissertation presents methods for using truncated-matrix multipliers and squarers in high-performance DSP hardware that allow area, delay, and power benefits to be achieved without compromising the quality of the system output due to error. Finite-impulse-response (FIR) filters, two-dimension discrete cosine transform and inverse discrete cosine transform (2-D DCT and IDCT) hardware accelerators, and function interpolators are studied. Unlike previous research, which only looks at the unit level, a system-level approach is taken to reduce the overall error of the system output. By taking a system-level approach, the output of the system can be improved significantly compared to only using unit-level techniques. System-level techniques including coefficient shifting, system-level constant correction, and error apportioning are developed. K. Cho, K. Lee, J. Chung, and K. Parhi, aLow Error Fixed-Width Modified Booth Multiplier, a in Proceedings of the IEEE ... and J. Kim, aLow-Error Fixed Width Squarer Design, a in Proceedings of the IEEE International Symposium on Circuits anbsp;...
|Title||:||Using Truncated-matrix Multipliers and Squarers in High-performance DSP Systems|
|Author||:||E. George Walters (III.)|
|Publisher||:||ProQuest - 2009|