VHDL for Engineers

VHDL for Engineers

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Suitable for use in a one- or two-semester course for computer and electrical engineering majors. VHDL for Engineers, First Edition is perfect for anyone with a basic understanding of logic design and a minimal background in programming who desires to learn how to design digital systems using VHDL. No prior experience with VHDL is required. This text teaches readers how to design and simulate digital systems using the hardware description language, VHDL. These systems are designed for implementation using programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The book focuses on writing VHDL design descriptions and VHDL testbenches. The steps in VHDL/PLD design methodology are also a key focus. Short presents the complex VHDL language in a logical manner, introducing concepts in an order that allows the readers to begin producing synthesizable designs as soon as possible.The efficiency of a FSM is a function of the efficiency of the state diagram used to represent it. State Diagram Editor A state diagram editor is an EDA software tool designed for graphically creating and editing state diagrams. A state diagramanbsp;...

Title:VHDL for Engineers
Author:Kenneth L. Short
Publisher:Prentice Hall - 2009


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