This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Am Most up-to-date coverage of design for testability. Am Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Am Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Am Lecture slides and exercise solutions for all chapters are now available. Am Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.... solutions, 725-726 I/O interface technology and trend, 720-724 overview, 719- 720 high-speed networks, 579-580 HIGHZ instruction, 574, 665, 666 hold cycle, 61 hold-time violation, 429 hot-carriers, 692 hot electron, 700 HTC (hierarchicalanbsp;...
|Title||:||VLSI Test Principles and Architectures|
|Author||:||Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen|
|Publisher||:||Academic Press - 2006-08-14|