This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif ... R. Nassif, and Duane Boning ISBN 978-0-387-30928-6 Low Power Methodology Manual: For System- on-Chip Design Michael Keating, ... Donhee Ham and Robert M. Westervelt ISBN 978-0-387-36836-8 SAT-Based Scalable Formal Verification Solutions Malay Ganaianbsp;...
|Title||:||Wafer Level 3-D ICs Process Technology|
|Author||:||Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif|
|Publisher||:||Springer Science & Business Media - 2009-06-29|